Semiconductor integrated circuit device

ABSTRACT

Prior known static random access memory (SRAM) cells are required that a diffusion layer be bent into a key-like shape in order to make electrical contact with a substrate with a P-type well region formed therein, which would result in a decrease in asymmetry leading to occurrence of a problem as to the difficulty in micropatterning. To avoid this problem, the P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NW 1  and are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supplying power to the substrate are formed in parallel to word lines in such a manner that one regions is provided per group of thirty two memory cell rows or sixty four cell rows.

BACKGROUND OF THE INVENTION

[0001] The present invention relates generally to semiconductor integrated circuit devices and, more particularly, to layout schemes of static random access memory (SRAM) cells. The invention also relates to semiconductor memory devices using such cells.

[0002] One-port SRAM cells with complementary metal oxide semiconductor (CMOS) configurations are typically designed so that each cell consists essentially of six separate transistors. An exemplary layout of such cells has been disclosed, for example, in JP-A-10-178110 (laid open on Jun. 30, 1998).

[0003] In the previously known SRAM cell layout, a semiconductive well region of P type conductivity with inverters formed therein is subdivided into two subregions, which are disposed on the opposite sides of an N-type well region while permitting a well boundary line to extend in a direction parallel to the bit lines.

[0004] The quest for higher integration and ultra-fine patterning techniques in modern memory devices requires an optical exposure apparatus or equipment to decrease the wave length of the beams used therein. To this end, the equipment is designed to employ exposure beams of shorter wavelengths, which have advanced from G line to I line, and then further to excimer lasers. Unfortunately, the requirements for micro-patterning architectures have grown more rapidly than technological advance in the trend of shortening wavelengths in such equipment. In recent years, it has been strictly required that micropatterning be done with the minimum device-feature length that shrinks to less than or equal to the wavelength of the exposure beam used. This minimum feature length shrinkage would result in a layout of IC components—particularly, memory cells—becoming more complicated in planar shape, which necessitates the use of irregular polygonal layout patterns including key-shaped components, in order to achieve the intended configuration of an on-chip circuitry with enhanced accuracy. This makes it impossible, or at least very difficult, to microfabricate ultrafine layout patterns while disadvantageously serving as the cause of the destruction of the symmetry of memory cells.

[0005] Regrettably, the prior art approach is associated with a need to curve or bend a diffusion layer into a complicated key-like shape for the purpose of making electrical contact with a substrate of the P-type well region. Thus, the prior art suffers from the problem of the degradation of the symmetrization of the cell layout pattern, making the successful achievement of microfabrication architectures for higher integration densities difficult.

SUMMARY OF THE INVENTION

[0006] In accordance with one aspect of the present invention, a semiconductor device is provided which comprises a first inverter including a first N-channel metal oxide semiconductor MOS transistor, and a first channel MOS transistor, a second inverter including a second N-channel MOS transistor and a second P-channel MOS transistor with an input terminal being connected to an output terminal of the first inverter and with an output terminal being connected to an input terminal of said first inverter, a third N-channel MOS transistor having a source connected to the output terminal of said first inverter, a drain connected to a first bit line, and also a gate connected to a word line, and a fourth N-channel MOS transistor having a source connected to the output terminal of said second inverter, a drain connected to a second bit line, and a gate connected to a word line, wherein the first and third N-channel MOS transistors are formed in a first P-type well region, wherein the diffusion layer has no curved or bent portions, while letting the direction of the layout be parallel to the boundary with respect to the first N-well region with the first and second P-channel MOS transistors formed therein, and wherein said second and fourth N-channel MOS transistors are formed in the second P-type well region, whose diffusion layer has no bent portions, while letting the layout direction be parallel to the boundary with respect to the first N-well region with the first and second P-channel MOS transistors formed therein.

[0007] The diffusion layer is arranged to have its outer shape, which mainly consists of straight line segments including the longest straight line portion, which lies parallel to the boundary with respect to the first N-well region with the first and second P-channel MOS transistors formed therein, and simultaneously in the case of defining a straight line acting as the center line extending parallel to such a boundary, the longest line portion is in linear symmetry with said center line; the second and fourth N-channel MOS transistors are formed in the second P-well region, whose diffusion layer is mainly arranged by straight line segments including its longest straight line portion that is parallel to the boundary with respect to the first N-well region with the first and second P-channel MOS transistors formed therein while allowing, when defining a straight line for use as the center line extending parallel to such a boundary, the line portion to be linearly symmetrical to the center line. At this time, in the case of employing the linear symmetrization scheme, complete linear symmetry will not always be required. Alternatively, slight nonsymmetry may also be permissible on a case-by-case basis. This nonsymmetry results from modifying the diffusion layer to have a shape in which its portions on the right and left sides of the center line are substantially the same in area as each other, by way of example.

[0008] In accordance with another aspect of this invention, a first polycrystalline silicon lead layer for use as the gate of said third N-channel MOS transistor and a second polycrystalline silicon lead layer for use as the gate of said first P-channel MOS transistor, and also as the gate of said first N-channel MOS transistor, are disposed in parallel to each other, wherein a third polycrystalline silicon lead layer for use as the gate of said fourth N-channel MOS transistor, and a fourth polycrystal-line silicon lead layer for use as the gate of said second N-channel MOS transistor, and also as the gate of said second P-channel MOS transistor are disposed in parallel to each other, and wherein the first and third polycrystalline silicon lead layers are connected via a contact to-a second layer which serves as a metal lead layer constituting the word lines.

[0009] In accordance with another aspect of the invention, the input terminal of said first inverter and the output terminal of said second inverter may be electrically connected together at a contact, whereas the input terminal of said second inverter and the output terminal of said first inverter are electrically connected together at a contact.

[0010] In accordance with yet another aspect of the invention, a power supply line connected to the first and second bit lines, the sources of said first and second P-channel MOS transistors, and a ground line connected to the sources of said first and second N-channel MOS transistors may be formed of a third layer serving as a metal lead layer lying parallel to a diffusion layer.

[0011] In accordance with a still another aspect of the invention, the first bit line formed of said third layer serving as a metal lead layer may be arranged so that it is between a power supply line formed of said third layer serving as a lead layer and a ground line as connected to the source of said first N-channel MOS transistor formed of said third layer serving as a metal lead layer whereas the second bit line formed of said third layer serving as a metal lead layer is between a power supply line formed of said third layer serving as a metal lead layer and a ground line as connected to the source of said second N-channel MOS transistor formed of said third layer serving as a metal lead layer.

[0012] In accordance with another aspect of the invention, the first and second bit lines and a power supply line connected to the sources of said first and second P-channel MOS transistors may be formed of a second layer serving as a metal lead layer, wherein word lines are formed of a third layer of metal lead layer, and wherein a ground line connected to the sources of said first and second N-channel MOS transistors is formed of the third layer and second layer serving as a metal lead layer.

[0013] In accordance with a still another aspect of the invention, memory cells are laid out into the form of an array, wherein contacts to a substrate of a P-type well region and a contact to a substrate of an N-type well region are linearly disposed within the array and at upper and lower portions of the array in a direction parallel to the word lines. Although the above is an example which causes two separate P-well regions to be disposed on the opposite sides of an N-well region, two N-well regions may be disposed on the opposite sides of a P-well region when the need arises.

[0014] In accordance with yet another aspect of the invention, a semiconductor device is provided which comprises a plurality of memory arrays, each including an array of memory cells having at least an N-type well region and a P-type well region, and at least one intermediate region between the memory arrays, wherein the N-type well region and P-type well region define therebetween a boundary with at least one straight line portion, and wherein a diffusion layer is formed in both the N-type well region and the P-type well region to have a planar shape of either (1) a rectangle having long sides extending-parallel to said straight line portion, or (2) a shape resulting from letting a plurality of rectangles having long sides extending parallel to the straight line portion be combined together via respective short sides thereof; or alternatively,

[0015] (1) a rectangle having long sides parallel to said straight line portion, or (2) a shape resulting from letting a plurality of rectangles having long sides parallel to said straight line portion be combined together, causing them to extend in the direction of the straight line.

[0016] At least in the memory array regions, bit lines are laid out in a direction parallel to the straight line portion, whereas word lines are disposed in a direction perpendicular to the straight portion. Preferably, in the intermediate region, at least one type of electrical lead is railed in a direction at right angles to the straight portion, and a lead (e.g. contact) is also formed with the purpose of making electrical contact between a power supply voltage lead and the diffusion layer as formed in the N-well region or P-well region. This lead may include a power supply lead, ground lead, or other potential leads.

[0017] The invention is particularly useful for those semiconductor memory devices having static RAM memory cells each consisting essentially of six separate transistors.

BRIEF DESCRIPTION OF THE DRAWINGS

[0018]FIG. 1 is a diagram showing an SRAM cell in accordance with Embodiment 1 of the present invention, for explaining a layout pattern of those contacts for connection between MOS transistors and those for connecting between MOS transistors and metal lead layers.

[0019]FIG. 2 is a diagram showing a layout of via holes of SRAM cells for connection between multilayered metal leads in accordance with Embodiment 1 of this invention.

[0020]FIG. 3 is a diagram showing a layout of memory cells and their associated peripheral circuitry in accordance with Embodiment 2 of the invention.

[0021]FIG. 4 is a diagram showing an SRAM cell in accordance with Embodiment 3 of the invention, for explaining a layout of those contacts for connection between MOS transistors and those for connection between MOS transistors and metal lead layers.

[0022]FIG. 5 is a diagram showing a layout of via holes of SRAM cells for connection between multilayered metal leads in accordance with Embodiment 3 of the invention.

[0023]FIG. 6 is a diagram showing an SRAM cell in accordance with Embodiment 4 of the invention, for explaining a layout of those contacts for connection between MOS transistors and those for connection between MOS transistors and metal lead layers.

[0024]FIG. 7 is a diagram showing a layout of via holes of SRAM cells for connection between muitilayered metal leads in accordance with Embodiment 3 of the invention.

[0025]FIG. 8 is a diagram showing an SRAM cell in accordance with Embodiment 5 of the invention, for explaining a layout of those contacts for connection between MOS transistors and those for connection between MOS transistors and metal lead layers.

[0026]FIG. 9 is a diagram showing a layout of via holes of SRAM cells for connection between muitilayered metal leads in accordance with Embodiment 5 of the invention.

[0027]FIG. 10 is a diagram showing an SRAM cell in accordance with Embodiment 6 of the invention, for explaining a layout of those contacts for connection between MOS transistors and those for connection between MOS transistors and metal lead layers.

[0028]FIG. 11 is a diagram showing a layout of via holes of SRAM cells for connection between multilayered metal leads in accordance with Embodiment 6 of the invention.

[0029]FIGS. 12a to 12 f are diagrams illustrating in cross-section some of major process steps in the manufacture of the semiconductor device in accordance with Embodiment 6 of the invention.

[0030]FIG. 13 is a diagram showing an SRAM cell in accordance with Embodiment 7 of the invention, for explaining a layout of those contacts for connection between MOS transistors and those for connection between MOS transistors and metal lead layers.

[0031]FIG. 14 is a diagram showing a layout of via holes of SRAM cells for use in connecting between multilayered metal leads in accordance with Embodiment 7 of the invention.

[0032]FIG. 15 is a diagram showing an SRAM cell in accordance with Embodiment 8 of the invention, for explaining a layout of those contacts for connection between MOS transistors and those for connection between MOS transistors and metal lead layers.

[0033]FIG. 16 is a diagram showing a layout of via holes of SRAM cells for connection between multilayered metal leads in accordance with Embodiment 8 of the invention.

[0034]FIG. 17 is a sectional view of a semiconductor device in accordance with Embodiment 8 of the invention.

[0035]FIGS. 18a to 18 f are diagrams illustrating in cross-section some of major process steps in the manufacture of a semiconductor device in accordance with Embodiment 9 of the invention.

[0036]FIGS. 19a to 19 g are diagrams illustrating in cross-section some of major process steps in the manufacture of a semiconductor device in accordance with Embodiment 10 of the invention.

DETAILED DESCRIPTION OF EMBODIMENTS

[0037] Several preferred embodiments of the semiconductor memory device in accordance with the present invention will be explained with reference to the accompanying drawings below.

[0038] <Embodiment 1>

[0039] Referring to FIGS. 1 and 2, SRAM cell layout MC embodying the invention. FIG. I illustrates well regions and diffusion layers plus a polycrystalline silicon interconnect lead layer, as well as contacts, all of which are formed in or over a semiconductor substrate FIG. 2 depicts a first layer serving as a metal lead layer, via holes 1, a second layer serving as a metal lead layer, via holes 2, and a third layer serving as a metal lead layer. Symbols used in FIGS. 1 and 2 are indicated at the lower part of FIG. 2.

[0040] An N-channel type MOS transistor TN1 formed in a P-type semiconductive well region PW1 and a P-channel type MOS transistor TP1 formed in an N-type well region NW1 constitute an inverter INV1. In addition, an N-channel MOS transistor TN2 formed in P-type well region PW2 and a P-channel MOS transistor TP2 formed in N-type well region NW1 constitute an inverter INV2.

[0041] An output node of the inverter INVL is electrically connected by a contact SC1 to an input node of the inverter INV2. An output of the inverter INV2 is electrically connected via a contact SC2 to an input of the inverter INV1.

[0042] An N-channel MOS transistor TN3 has a drain electrode connected to a bit line BL, a source electrode connected to a drain of the N-channel MOS transistor TN1, and a gate electrode connected to a word line WD. Similarly, an N-channel MOS transistor TN4 has a drain electrode connected to a bit line BL2, a source electrode connected to a drain of the N-channel MOS transistor TN2, and a gate electrode connected to a word line WD.

[0043] The N-channel MOS transistor TN1 and the N-channel MOS transistor TN3 are formed over a diffusion layer LN1, whereas the N-channel MOS transistor TN2 and the N-channel MOS transistor TN4 are formed over a diffusion layer LN2. The P-channel MOS transistor TP1 is formed over a diffusion layer LP1, whereas the P-channel MOS transistor TP2 is formed over a diffusion layer LP2.

[0044] As the diffusion layers (LN1, LN2, LP1, LP2) are straight lines with no curved portions, any pattern correction at the folded portions is no longer necessary, resulting in the balance between nodes being improved. In case the memory cells are laid out into the form of an array, the diffusion layers become four separate straight lines extending parallel to the bit lines (BL1, BL2).

[0045] In addition, a polycrystalline silicon interconnect lead layer FG3 to be used the gate electrode of the N-channel MOS transistor TN3 and a polycrystalline silicon lead layer FG4 to be used as the gate electrode of the N-channel MOS transistor TN4 are connected to word lines WL, which are formed of-the second metal lead layer in a vertical direction to the bit lines (BL1, BL2) A polycrystalline silicon interconnect lead layer FG1 to be used as the gate electrode of the N-channel Mbs transistor TN1 and the P-channel MOS transistor TP1 and a polycrystalline silicon interconnect lead layer FG2 to be used as the gate electrode of the N-channel MOS transistor TN2 and the P-channel MOS transistor TP2, plus the polycrystalline silicon lead layers (FG3, FG4), are disposed in parallel to the word lines.

[0046] The N-channel MOS transistor TN1 has its source electrode connected to a ground potential line Vss1 that is formed of the third layer serving as a metal lead layer, whereas a source electrode of the N-channel MOS transistor TN2 is connected to a ground line Vss2 that is formed of the third layer serving as a metal lead layer. In addition, source electrodes of the P-channel MOS transistors (TP1, TP2) are connected to a power supply voltage line Vcc1 which is formed of the third layer serving as a metal lead layer.

[0047] The bit line BL1 is located midway between the power supply voltage line Vcc1 and ground line Vss1, whereas bit line BL2 is between the supply voltage line Vcc1 and ground line Vss2. This structure makes it possible to reduce cross-couple noises occurring between bit lines, which advantageously lowers voltages while increasing operation speeds.

[0048] In addition, it is considered that, in case a contact is formed on an n⁻ layer through the partial cutaway of side spacers during the etching of contact holes, a leakage current from the contact via the n-layer to the substrate may be produced. When a contact is formed for connection between a polycrystalline silicon lead layer and a diffusion layer, the distance between the diffusion layer LP2 and polycrystalline silicon lead layer FG1 should be greater than the length of a side spacer to thereby eliminate the formation of an n⁻ layer on the polycrystalline silicon lead layer FG1 side of the diffusion layer LP2, which in turn makes it-possible to prevent a flow of leakage current.

[0049] <Embodiment 2>

[0050] Turning to FIG. 3, an exemplary case is shown where the memory cells MC of Embodiment 1 are laid out into the form of an array. Symbols used herein are the same as those indicated at the lower part of FIG. 2.

[0051] The memory cells MC are organized into an array of 256 rows and 128 columns, by way of example. In view of the fact that these memory cells in Embodiment 1 are shorter in length in the longitudinal direction of the bit lines, the total length of the 256 rows of memory cells along the bit lines is shorter than that of prior art devices, thus increasing resultant operation speeds. Neighboring memory cells MC are disposed in linear symmetry with respect to a “y” axis whereas upper and lower adjacent memory cells MC are in linear symmetry with an “x” axis. In addition, specified regions ST for use in supplying more than one power supply voltage to the substrate are formed at the intermediate part of the array in such a manner that the regions ST extend parallel to word lines WD. One example is that the regions ST are laid out in units of 32-row groups. Another example is that regions ST are disposed in units of 64-row groups.

[0052] An electrical lead Vbn for supplying a voltage potential to the P-well regions (PW1, PW2) and a lead Vbp for supplying a voltage to the N-well region NW1 are formed to lie parallel to word lines. The lead Vbn may be coupled to the ground potential Vss or, alternatively, any voltage may be applied thereto which is potentially different from the ground Vss. The lead Vbp may be coupled to the power supply voltage Vcc or, alternatively, any voltages potentially different from the Vcc may be applied thereto.

[0053] Note that in each region ST, a power supply voltage line Vcc for potentially “reinforcing” a power supply voltage line Vcc1 is formed in parallel to word lines while, allowing a ground potential line Vss for potentially reinforcing ground potentials (Vss1, Vss2) to be formed in parallel to the word lines.

[0054] Also note that the ground lines (Vss1, Vss2) are disposed in a direction perpendicular to the word lines WD, whereby upon selecting a single word line a voltage potential is supplied from the pair of ground lines to a respective one of those memory cells operatively associated with this selected word line so that any possible noises occurring at such voltage lines are reduced, thereby advantageously speeding an access operation while potentially reducing any voltages concerned.

[0055] Furthermore, the memory cells MC used are great in width in the word line direction so that the layout design of sense amplifiers AMP is made easier, thereby avoiding the need to lay out one sense amplifier for two adjacent columns of memory cells, which in turn makes it possible to permit one sense amplifier to be laid out at each column. Additionally, a word line driver circuit wddrv becomes fiat in layout as compared to previously prior known ones.

[0056] <Embodiment 3>

[0057]FIGS. 4 and 5 show a SRAM cell layout MC2 in accordance with Embodiment 3. Symbols as used in FIGS. 4-5 are the same as those in FIG. 2. Memory cell MC2 of Embodiment 3 is similar to the memory cell MC of Embodiment 1, with the exception that, as compared to Embodiment 1, in which the diffusion layer (LN1, LN2) is formed into a “IT”-like planar shape, which resembles a Japanese battledore plate called “hagoita,” the diffusion layer (LN3, LN4) of Embodiment 4 is of a rectangular shape, and the contacts (SC1, SC2) are replaced with contacts (SC3, SC4) in the first layer serving as metal lead layers (M11, M12).

[0058] To attain stability, memory cells are typically designed so that the gate width of the N-channel MOS transistors (TN1, TN2) is one and a half times greater than that of the N-channel MOS transistors (TN3, TN4) However, in this case, the shape of the diffusion layers resembles a T-like planar shape, as shown in Embodiment 1, which in turn requires extra techniques, including pattern correction procedures such as optical proximity effect correction (OPC) processes. Additionally, this would result in the degradation of the balance between transistors. In contrast, Embodiment 3 is such that the diffusion layers (LN3, LN4) are designed to have a rectangular shape whereby the micro-patterning required becomes easier while at the same time enabling an improvement in balance between transistors. Note, however, that the resultant gate width ratio becomes as large as 1.0 time, which in turn requires that the so-called cell ratio be increased by making different drivabilities therebetween. This is attainable by letting the N-channel MOS transistors (TN3, TN4) be greater in oxide film thickness than the N-channel MOS transistors (TN1, TN2), by increasing the gate length thereof, or by increasing the threshold value, or by lowering the impurity concentration of lightly-doped drain regions for relaxation of electric fields.

[0059] In addition, Embodiment 3 is arranged to employ a contact SC3 and a first layer serving as a metal lead layer M11 in place of the contact SC1 used in Embodiment 1 for connection between the output of the inverter INVL and the input of the inverter INV2. With such an arrangement, any curved or bent contacts are no longer necessary, thereby avoiding the need for pattern correction (OPC) or the like.

[0060] <Embodiment 4>

[0061]FIGS. 6 and 7 show an SRAM cell layout MC3 in accordance with Embodiment 4. The symbols used in FIGS. 6-7 are the same as those in FIG. 2. Memory cell MC3 of Embodiment 4 is similar to the memory cell MC2 of Embodiment 3, except that the polycrystalline silicon lead layers (FG5, FG6, FG7, FG8) are designed to have a rectangular planar shape. With this cell, any bent/folded portions are absent, thus removing the need for any additional pattern correction procedures including OPC processes, which in turn improves the balance between transistors.

[0062] <Embodiment 5>

[0063]FIGS. 8 and 9 show an SRAM cell layout MC4 in accordance with Embodiment 5. An explanation of the symbols used in FIGS. 8 and 9 is given at the lower part of FIG. 8. Memory cell MC4 of Embodiment 5 is different in lead structure from the memory cell MC of Embodiment 1.

[0064] Bit lines (BL3, BL4) and power supply line Vcc2 are formed by the use of a second layer serving as. a metal lead layer. A word line WD1 and ground lines (Vss5, Vss6) are formed using a third layer serving as a metal lead layer in a perpendicular direction to the bit lines. Ground lines (Vss3, Vss4) are formed using a fourth layer serving as a metal lead layer in a direction parallel to the bit lines.

[0065] A global bit line GB is the electrical interconnect lead that is used in the case that the bit lines are of a hierarchical configuration. The global bit line GB and bit lines (BL3, BL4) are shielded by the third layer serving as a metal lead layer, thus enabling the prevention of any possible cross-couple noises. Additionally, the use of ground lines (Vss3, Vss4) makes it possible to prevent the occurrence of crosscouple noises between global bit lines GB.

[0066] <Embodiment 6>

[0067]FIGS. 10 and 11 show an SRAM cell layout MC5 in accordance with embodiment 6. An explanation of the symbols used in FIGS. 10-11 is given at lower part of FIG. 11. Memory cell MC5 of Embodiment 6 is different from the memory cell MC of Embodiment 1 in the structure of the so-called three-layered contacts, each of which is for connection between a gate electrode and its associated diffusion layer.

[0068] Although in Embodiment 1 a gate electrode is connected to a diffusion layer via “L”-like contacts SC1 and SC2, Embodiment 6 is arranged so that the gate electrode is connected to the diffusion layer via silicide in connect regions SS1 and SS2. This makes it unnecessary to bend or curve the individual contact into the L-like shape in order to connect the gate electrode to the diffusion layer, which in turn makes it possible to provide “I”-like rectangular contacts SC5, SC6. No folded/bent portions are present in the contacts used, which eliminates the need for pattern correction (OPC).

[0069]FIGS. 12a-12F show a practical example of the process steps which can be used in manufacturing a device structure employing the connect regions SS1 and SS2, each for connection between a gate electrode and a diffusion layer associated therewith via silicide. Note here that FIGS. 12a-12 f are cross-sectional views, each indicating a profile as taken along line A-A1 in FIG. 10, with its right side corresponding to the side “A” and with its left side corresponding to “A1.”

[0070] Fabricate a gate electrode FG made of a chosen polycrystalline silicon material (see FIG. 12a).

[0071] Form a heavily-doped diffusion layer PM of a specified conductivity type-here, a P type (FIG. 12b).

[0072] Form side spacers made of silicon nitride (SiN) by chemical vapor deposition (CVD) techniques on the side-walls of the resultant gate electrode FG (FIG. 12c).

[0073] Make use of a resist RG to etch away only one of the SiN side spacers, which resides on an active region side under a prespecified condition that enables etching treatment of a silicon nitride film and oxide film at increased selectivity (FIG. 12d).

[0074] Fabricate a heavily-doped P (P+) type diffusion—layer P+.

[0075] After having removed through etching a certain part of the oxide film SiO that lies in the active region that is not covered by any overlying gate electrode FG, deposit a high-melting-point metal such as refractory metal including, but not limited to, cobalt (Co); then, anneal the resultant structure to thereby selectively form silicide on the poly-silicon gate electrode and diffusion layer (FIG. 12f). At this time, a-side-wall of the gate electrode and the diffusion layer are connected together by this silicide.

[0076] <Embodiment 7>

[0077]FIGS. 13 and 14 show an SRAM cell layout MC6 in accordance with Embodiment 7. An explanation of the symbols used in FIGS. 13-14 is the same as that given at the lower part of FIG. 11. Memory cell MC6 of Embodiment 7 is similar to the memory cell MC5 of Embodiment 6, with the contacts (SC5, SC6) being replaced with contacts (SC7, SC8) in the first layer serving as metal lead layers (M11, M12).

[0078] With Embodiment 7, all of the contacts used therein are capable of being designed to have a square planar shape, thus avoiding the need for pattern correction (OPC).

[0079] <Embodiment 8>

[0080]FIGS. 15 and 16 show an SRAM cell layout MC7 in accordance with Embodiment 8. An explanation of the symbols used in FIGS. 15-16 is given at the lower part of FIG. 16. Memory cell MC7 of Embodiment 8 is similar to the memory cell MC of Embodiment 1, with the contacts (SC1, SC2) being replaced with local interconnect nodes (L11, L12), and also with the word lines being modified in such a manner that these are formed in the first layer serving as a metal lead layer rather than in the second layer serving as a metal lead layer while also modifying the bit lines, power supply, and ground lines from the third layer serving as a metal lead layer to the second layer serving as a metal lead layer. FIG. 17 depicts a sectional view taken along line A-B of FIGS. 15-16.

[0081] Embodiment 1 suffers from limitations, such as an inability to dispose the first layer of metal leads over the contacts SC1 and SC2, due to the fact that these contacts SC1 and SC2 are formed of the same layer as the remaining contacts used. In contrast, Embodiment 8 is specifically arranged to employ the local interconnect nodes L11 and L12, formed in a separate layer from the contacts, thus making it possible to dispose the first layer serving as a metal lead layer at the upper part, which in turn makes it possible to reduce by one the requisite number of metal lead layers when compared to Embodiment 1.

[0082] <Embodiment 9>

[0083] A process flow of major steps in the manufacture of a three-layer contact section of Embodiment 9 is shown in FIGS. 18a-18 f. Embodiment 9 is an example of the process for fabrication of the three-layer contact section as used in Embodiments 1, 3-5 and 8.

[0084] Modern LSIs in recent years are typically designed so that micropatterning is done to form contact holes by high-selectivity etching techniques with a silicon nitride film, or else used as a stopper to ensure that any unwanted over-etching occurs at filed oxide films, even when contacts are offset in position from diffusion layers and/or gate electrodes due to the presence of possible alignment errors during photolithographical patterning processes. In such cases, gate electrodes are formed to have reduced electrical resistivities by the use of the so-called silicide processes. It is possible to obtain the intended electrical conduction between a contact lying over a gate electrode and a contact overlying a diffusion layer, even when the both contacts are fabricated at a time due to the fact that the contact holes required are fabricated after the completion of a procedure having the steps of forming silicide through exposure of selected portions overlying diffusion layers and gate electrodes after having formed such diffusion layers, depositing thereover a silicon nitride film for use as an etching stopper, and then further depositing thereover an interlayer dielectric film. On the contrary, in the case of either the traditionally widely employed polycide gate electrodes or the polymetal gate electrodes that have been developed and announced recently, residual portions of an insulative film such as an oxide film can overlie gate electrodes thereby preventing the exposure of these gate electrodes prior to deposition of a silicon nitride film acting as the etch stopper. Accordingly, whenever an attempt is made to form the intended contacts through the deposition of a silicon nitride film thereover, the oxide film behaves to partly reside at the bottom of a respective one of those contacts overlying the gate electrodes, which makes it impossible, or at least very difficult to provide the electrical conduction required. Embodiment 9 is for enabling the achievement of electrical conduction of such contacts overlying gate electrodes by the previous removal of any silicon nitride film portions overlying gate electrodes at a specified part at which contact holes will be defined.

[0085] An explanation will now be given of the process flow in the manufacture of Embodiment 9 with reference to FIGS. 18a-18 f below.

[0086] After having fabricated a gate electrode and a diffusion layer P+, deposit a silicon nitride film SiN for use as an etch stopper (FIG. 18a). The gate electrode is a lamination of polycrystalline silicon PolySi and tungsten W, with an oxide film SiO being further multilayered thereon as a protective film.

[0087] Remove by dry etching techniques a specified part of the silicon nitride film at locations for the definition of a contact hole overlying the gate electrode (FIG. 18b).

[0088] Deposit a TEOS film and others by plasma CVD methods to thereby form an interlayer dielectric film (FIG. 18c).

[0089] Let a selected portion of the oxide film at a contact opening portion be etched away by high selective dry etching techniques (FIG. 18d) Owing to such high selective etching, the silicon nitride film remains free from etch treatment and thus acts as a stopper. Since there is no stopper at the portion overlying the gate electrode from which the silicon nitride film has been removed in advance, this portion will be fully etched to the upper part of the gate electrode. This permits electrical conduction to occur also on the gate electrode.

[0090] Remove the silicon nitride film by dry etching techniques (FIG. 18e). Deposit a chosen metal, such as tungsten in the resulting contact hole, thereby forming a buried plug (FIG. 18f).

[0091] <Embodiment 10>

[0092] Turning to FIGS. 19a-19 g, a process flow in the manufacture of the three-layer contact section of Embodiment 10 is shown. Embodiment 10 is one example of the process for forming the three-layer contact section of Embodiments 1, 3-5 and 8.

[0093] A difference in the process flow of Embodiment 10 from that of Embodiment 9 is that more than one portion of the oxide film at a specified location at which a contact hole is to be opened over the gate electrode has been removed in advance prior to the deposition of a silicon nitride film to be used as the etch stopper.

[0094] The fabrication process flow of Embodiment 10 will be explained with reference to FIGS. 19a-19 g below.

[0095] Fabricate a gate electrode and a diffusion layer P+ (FIG. 19a). The gate electrode is a lamination of polycrystalline silicon PolySi and tungsten W, with an oxide film SiO further stacked thereon as a protective film.

[0096] Remove by dry etching techniques a specified part of the silicon nitride film at the location for the definition of a contact hole overlying the gate electrode, thus letting the gate electrode be exposed at its upper part (FIG. 19b).

[0097] Deposit a silicon nitride film SiN as an etch stopper (FIG. 19c).

[0098] Deposit a TEOS film by plasma CVD methods to thereby form an interlayer dielectric film (FIG. 19d).

[0099] Let a portion of the oxide film at the contact opening portion be etched away by high selective dry etching techniques (FIG. 19e) Due to such high selective etching, the silicon nitride film remains free from etching treatment and thus acts as the stopper.

[0100] Remove the silicon nitride film by dry etching techniques (FIG. 19f) A certain portion from which the oxide film overlying the gate electrode has been removed prior to the deposition of the silicon nitride film is thus exposed at this time, which permits electrical conduction to occur also in the gate electrode.

[0101] Deposit a chosen metal such as tungsten in the resultant contact hole, thereby forming a buried plug (FIG. 19g).

[0102] In accordance with the embodiments stated above, any diffusion layers used therein are specifically designed to have a simplified planar shape, excluding unnecessarily complicated shapes, which may in turn facilitate micro-patterning processes. 

What we claim is:
 1. A semiconductor memory device comprising: a first and second bit line; a first word line; and a memory cell having a first inverter including a first N-channel MOS transistor and a first P-channel MOS transistor, a second inverter including a second N-channel MOS transistor and a second P-channel MOS transistor with an input terminal being coupled to an output terminal of said first inverter and with an output terminal being coupled to an input terminal of said first inverter, a third N-channel MOS transistor having a source/drain path coupled between the output terminal of said first inverter and the first bit line, and a fourth N-channel MOS transistor having a source/drain path coupled between the output terminal of said second inverter and the second bit line; wherein said first and third N-channel MOS transistors are formed in a first P-type well region, wherein said second and fourth N-channel MOS transistors are formed in a second P-type well region, wherein said first and second P-channel MOS transistors are formed in an N-type well region which lies between first and second P-type well region, and wherein the first P-type well region includes a diffusion layer, wherein an outer shape of the diffusion layer, defined by an isolation layer which extends along the entirety of each of the longitudinal sides of the diffusion layer, is substantially linearly symmetric relative to a line extending in a first direction through said P-type well region, and wherein the boundary of said first P-type well region and said N-type well region extends in said first direction.
 2. A semiconductor memory device according to claim 1: wherein said outer shape of the diffusion layer in the first P-type well is a rectangle.
 3. A semiconductor memory device according to claim 1: wherein said outer shape of the diffusion layer in the first P-type well is an outer shape of a combination of rectangles.
 4. A semiconductor memory device according to claim 1: wherein said first bit line lies between a first power supply line and a first ground line, and wherein said second bit line lies between said first power supply line and a second ground line, and wherein said first ground line is coupled to the source of said first N-channel MOS transistor and said second ground line is coupled to the source of said second N-channel MOS transistor.
 5. A semiconductor memory device according to claim 4, wherein said first bit line, said first power supply line, and said first and second ground lines are formed metal layers having the same level at the same metalization level.
 6. A semiconductor memory device according to claim 1, wherein the width of the gate of the first N-channel MOS transistor is larger than the width of the gate of the third N-channel MOS transistor.
 7. A semiconductor memory device according to claim 1, wherein said first word line lies in a metalization level between the substrate and the first and second bit lines.
 8. A semiconductor memory device comprising: a first, second, third and fourth bit lines; a first word line; and a first memory cell having a first inverter including a first N-channel MOS transistor and a first P-channel MOS transistor, a second inverter including a second N-channel MOS transistor and a second P-channel MOS transistor with an input terminal being coupled to an output terminal of said first inverter and with an output terminal being coupled to an input terminal of said first inverter, a third N-channel MOS transistor having a source/drain path coupled between the output terminal of said first inverter and said first bit line, and a fourth N-channel MOS transistor having a source/drain path coupled between the output terminal of said second inverter and said second bit line; a second memory cell having a third inverter including a fifth N-channel MOS transistor and a third P-channel MOS transistor, a fourth inverter including a sixth N-channel MOS transistor and a fourth P-channel MOS transistor with an input terminal being coupled to an output terminal of said third inverter and with an output terminal being coupled to an input terminal of said third inverter, a seventh N-channel MOS transistor having a source/drain path coupled between the output terminal of said third inverter and said third bit line, and a eighth N-channel MOS transistor having a source/drain path coupled between the output terminal of said fourth inverter and said fourth bit line; wherein said first, third, fifth, and seventh N-channel transistors are formed in a first P-type well region, wherein said second and fourth N-channel MOS transistors are formed in a second P-type well region, wherein said first and second P-channel MOS transistors are formed in a first N-type well region which lies between first and second P-type well regions, wherein said sixth and eighth N-channel MOS transistors are formed in a third P-type well region, wherein said third and fourth P-channel MOS transistors are formed in a second N-type well region which lies between first and third P-type well regions, and wherein a first active region includes the source and drain regions of said first and third N-channel MOS transistors and a second active region includes the source and drain regions of said fifth and seventh N-channel MOS transistors, wherein said first and second active regions are isolated from each other by an isolation layer.
 9. The semiconductor memory device according to claim 8, wherein said isolation layer is SGI.
 10. The semiconductor memory device according to claim 8, wherein said third, fourth, seventh, and eighth N-channel MOS transistors are coupled to said first word line, wherein the source of said first and fifth N-channel MOS transistors are coupled to each other via first wiring line feeding a first operation potential, and wherein said first wiring line is formed on the same metalization level of said a first, second, third and fourth bit lines.
 11. The semiconductor memory device according to claim 10, wherein the source of said first and second P-channel MOS transistors are coupled to each other via second wiring line feeding a second operation potential, wherein said second wiring line is formed on the same metalization level of said a first wiring line, and wherein said first bit line is laid between said first and second wiring line.
 12. The semiconductor memory device according to claim 8, wherein the gate width of said first N-channel MOS transistor is larger than the gate width of said third N-channel MOS transistor.
 13. The semiconductor memory device according to claim 12, wherein the outershape of the first active region in the first P-type well is substantially linearly symmetric relative to a line in said first P-type well extending in a first direction, wherein the outershape of the second active region in the second P-type well is substantially linearly symmetric relative to a line in said second P-type well extending in said first direction, and wherein the boundary of said first P-type well region and N-type well region extends in said first direction.
 14. A semiconductor memory device according to claim 1, wherein a first polycrystalline silicon lead layer for use as the gate of said third N-channel MOS transistor and a second polycrystalline silicon lead layer for use as the gate of said first P-channel MOS transistor and also as the gate of said first N-channel MOS transistor are disposed in parallel to each other, wherein a third polycrystalline silicon lead layer for use as the gate of said fourth N-channel MOS transistor and a fourth polycrystalline silicon lead layer for use as the gate of said second N-channel MOS transistor and also as the gate of said second P-channel MOS transistor are disposed in parallel to each other, and wherein the first and third polycrystalline silicon lead layers are connected via a contact to a second layer of a metal lead layer constituting said first word line.
 15. A semiconductor memory device according to claim 1, wherein the input terminal of said first inverter and the output terminal of said second inverter are electrically connected together at a contact whereas the input terminal of said second inverter and the output terminal of said first inverter are electrically connected together at a contact.
 16. A semiconductor device comprising first and second inverters with an output of each inverter being as an input of a remaining inverter, a first switch connected to a connection node between an output of the first inverter and an input of the second inverter, and a second switch connected to a connection node between an input of said first inverter and an output of said second inverter, wherein said semiconductor device has an N-type well region and first and second P-type well regions as disposed on opposite sides of said N-type well region, a diffusion layer formed in each of said N-type well region and said first and second P-type well regions is arranged in planar shape to have one of (1) a shape consisting essentially of a single rectangle having long sides in an elongate direction of a boundary line of said N-type well region and said first and second P-type well regions and (2) a shape resulting from combination of a plurality of rectangles in the elongate direction of the boundary line of said N-type well region and said first and second P-well regions, the rectangles having long sides in said elongate direction.
 17. A semiconductor device according to claim 16, wherein the diffusion layer formed in said N-type well region and P-type regions has its planar shape resembling a single rectangle having long sides in the elongate direction of boundary lines of said N-type well region and said first and second P-type well regions.
 18. A semiconductor device according to claim 16, wherein the diffusion layer formed in said N-type well region or P-type region has its planar shape of a combined form as resulting from combination of a first rectangle having long sides in the elongate direction of boundary lines of said N-type well region and said first and second P-type well regions along with a short side of a first length and a second rectangle having long sides in the elongate direction of the boundary lines of said N-type well region and said first and second P-type well regions along with a short side of a second length, the combination being in the elongate direction of said boundary lines. 